1. Field of Invention
Embodiments of the present invention generally relate to semiconductor package structures and methods of fabricating the same. More particularly, embodiments of the present invention relate to a semiconductor package structure and a method of fabricating the same which facilitates changing the design of a structure of a chip selection unit.
2. Description of the Related Art
A semiconductor fabrication process includes a front-end process for fabricating integrated circuit (IC) chips on a wafer using photolithography, deposition, and etching processes and a back-end process for assembling and packaging the respective IC chips. Four significant functions of the packaging process are as follows:
1. Protection of the IC chips from environment and handling damage.
2. Formation of interconnection lines used to transmit input/output signals from/to the IC chips.
3. Physical support of the IC chips.
4. Dissipation of heat from the IC chips.
In addition, with an increase in the integration density of semiconductor devices and the spread of portable electronic devices, improved properties (e.g., enhancement of electrical performance and reductions of cost, weight and thickness) are being demanded. In order to satisfy these technical requirements, a Package on Package (PoP), a chip-scale package (CSP), and a wafer-level package (WLP) have been recently developed. Particularly, a PoP technique for electrically connecting stacked chips using through-vias is being expected as a technique suitable for providing high performance and a small form factor. Meanwhile, a PoP including through-vias requires a chip selection unit to select a predetermined chip because the through-vias are interconnection lines shared among a plurality of chips.
FIGS. 1 and 2 are plan and perspective views, respectively, of a conventional PoP having a chip selection unit.
Referring to FIGS. 1 and 2, a plurality of semiconductor chips C1, C2, C3, and C4, each including an internal circuit, are stacked. The semiconductor chips C1 to C4 include chip pads 20 connected to internal circuits, redistribution structures 30 connected to the chip pads 20, and through-vias 10 formed through the semiconductor chips C1 to C4. The through-vias 10 are formed in an outer portion of each of the semiconductor chips C1 to C4 and electrically connect the semiconductor chips C1 to C4 in a vertical direction. Thus, the through-vias 10 are stacked in a vertical direction with respect to the top surfaces of the semiconductor chips C1 to C4 and are used to form a vertical interconnection line of the PoP.
The through-vias 10 are electrically connected to the chip pads 20 and the internal circuits through the redistribution structures 30. Thus, internal circuits of the semiconductor chips C1 to C4 are commonly connected in parallel to the vertical interconnection line consisting of the stacked through-vias 10. Therefore, chip selection units 90 are required to selectively operate a predetermined semiconductor chip as described above.
According to the conventional art, each of the chip selection units 90 includes chip selection vias 11 to 14, a chip selection pad 25 connected to a chip selection circuit used for selecting a chip, and a chip selection line 31, 32, 33, or 34 used for connecting one of the chip selection vias 11 to 14 and the chip selection pad 25. Accordingly, the chip selection vias 11 to 14 are formed using the same process as the through-vias 10, the chip selection pad 25 is formed using the same process as the chip pads 20, and the chip selection lines 31 to 34 are formed using the same process as the redistribution structures 30. Also, each chip selection line 31 to 34 has a different structure according to the stacked order of the corresponding one of the semiconductor chips C1 to C4, as shown in FIGS. 1 and 2. For example, the chip selection line 31 of the first semiconductor chip C1 is connected only to the first chip selection via 11 and the chip selection line 32 of the second semiconductor chip C2 is connected only to the second chip selection via 12. As a result, each of the chip selection units 90 has a different structure according to the stacked order of the corresponding one of the semiconductor chips C1 to C4.
According to the conventional art, the structure of each of the chip selection units 90 is determined in a chip designing process. Specifically, each of the chip selection lines 31 to 34 and the redistribution structure 30 are formed using a different photo mask as an etch mask according to the stacked order of the corresponding one of the semiconductor chips C1 to C4. However, determining the structure of each of the chip selection units 90 in the chip designing process tends to deteriorate the flexibility of the packaging process. As a result, it is not easy to change the chip designing process for various reasons. For example, when a semiconductor chip connected to a predetermined chip selection via is added, the chip selection units 90 of all the semiconductor chips C1 to C4 need to be changed because of fixed structures of the chip selection units 90. However, to change of the chip selection units 90, photo masks used to form the redistribution structures 30 must also be changed. As a result, the cost and time associated with fabricating a PoP may be undesirably increased.
Furthermore, even if the semiconductor chips C1 to C4 are of the same configuration, the stacked order of the semiconductor chips C1 to C4 cannot be arbitrarily changed due to the fixed structures of the chip selection units 90. Thus, in the event that there is a supply shortage of a particular semiconductor chip, shipment of PoP devices incorporating the particular semiconductor chip may be delayed.